Saravanakumar, U., P Suresh, and S.P Vimal. “Low-Power, Low-Latency Transceiver Design Using D-TGMS Flip-Flop for on-Chip Interconnects”. International Journal of Engineering & Technology 7, no. 1 (January 29, 2018): 106–109. Accessed November 22, 2024. https://sciencepubco.com/index.php/ijet/article/view/8730.