Saravanakumar U, Suresh P, Vimal S. Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects. IJET [Internet]. 2018 Jan. 29 [cited 2024 Nov. 22];7(1):106-9. Available from: https://sciencepubco.com/index.php/ijet/article/view/8730