SAPNA KUMARI, C.; PRASAD, K. V. Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes. International Journal of Engineering & Technology, [S. l.], v. 7, n. 1.5, p. 126–134, 2017. DOI: 10.14419/ijet.v7i1.5.9134. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/9134.. Acesso em: 5 dec. 2024.