TOLENTINO, Lean Karlo; PADILLA, Maria Victoria; SERFA JUAN, Ronnie. FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code. International Journal of Engineering & Technology, [S. l.], v. 7, n. 3, p. 1008–1013, 2018. DOI: 10.14419/ijet.v7i3.12681. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/12681.. Acesso em: 24 nov. 2024.