KATHIRVELU, M.; BINDU, Hima. Design and Implementation of Low Power, Area Efficient Full Adder for High Performance Digital Circuit Applications. International Journal of Engineering & Technology, [S. l.], v. 7, n. 3.20, p. 584–587, 2018. DOI: 10.14419/ijet.v7i3.20.22946. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/22946.. Acesso em: 22 nov. 2024.