NAGA GANESH, A.; CHOLINES PEDAPUDI, Michael; V. APPARAO, N.; ., . Design a Glitch Tolerant Adiabatic Dynamic Logic Circuits for Cryptography. International Journal of Engineering & Technology, [S. l.], v. 7, n. 4.19, p. 402–406, 2018. DOI: 10.14419/ijet.v7i4.19.23173. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/23173.. Acesso em: 22 nov. 2024.