DUTTA, Umesh; K. SONI, M; PATTANAIK, Manisha. Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications. International Journal of Engineering & Technology, [S. l.], v. 7, n. 4, p. 2263–2270, 2018. DOI: 10.14419/ijet.v7i4.12352. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/12352.. Acesso em: 2 may. 2024.