SASIPRIYA, P; S KANCHANA BHAASKARAN, V. Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL). International Journal of Engineering & Technology, [S. l.], v. 7, n. 3, p. 1548–1551, 2018. DOI: 10.14419/ijet.v7i3.14632. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/14632.. Acesso em: 6 may. 2024.