Sapna Kumari, C., and K. V. Prasad. “Analysis of Power Reduction and Implementation on FPGA for AES-128bits Using BEDT Schemes”. International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 126–134. Accessed December 5, 2024. https://sciencepubco.com/index.php/ijet/article/view/9134.