TOLENTINO, Lean Karlo, Maria Victoria PADILLA, and Ronnie SERFA JUAN. “FPGA-Based Redundancy Bits Reduction Algorithm Using the Enhanced Error Detection Correction Code”. International Journal of Engineering & Technology 7, no. 3 (June 23, 2018): 1008–1013. Accessed November 24, 2024. https://sciencepubco.com/index.php/ijet/article/view/12681.