M S, Harish M S, and Jayadevappa D. “Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog”. International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373–382. Accessed November 22, 2024. https://sciencepubco.com/index.php/ijet/article/view/23810.