T, Sridhar, and Dr A. S. R Murty. “Low Power Driver Receiver Topology With Delay Optimization for on-Chip Bus Interconnects”. International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 180–184. Accessed May 3, 2024. https://sciencepubco.com/index.php/ijet/article/view/18554.