Chand Naguboina G, Anusudha K, Sravya T. Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx. IJET [Internet]. 2018 Nov. 26 [cited 2024 Nov. 24];7(3.29):769-74. Available from: https://sciencepubco.com/index.php/ijet/article/view/21656